Programmable logic device with ganged output pins
US5023606A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 1989 |
| Grant date | Jun 11, 1991 |
| Priority date | — |
| Expiry date | May 9, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit. Output pins connect directly to outputs of functional units. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by EPROM, or EEPROM switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.