Side wall contact in a nonvolatile electrically alterable memory cell
US5023694A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 1988 |
| Grant date | Jun 11, 1991 |
| Priority date | — |
| Expiry date | Aug 3, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A nonvolatile integrated circuit memory cell (10) is provided which is smaller in size than conventional memory cells and uses only two layers of polysilicon with floating gate portion (50) of the memory cell formed partly from a first polysilicon layer (20) and partly from second polysilicon layer (26), contact between the two portions being made using residual polysilicon bridge or overlapping portion (34) between the two layers. The invention enables programming and erase tunneling oxides to be formed in a single step while maximizing the capacitive coupling between the floating gate (50) and the substrate (12) by forming a silicon dioxide layer (102) between the floating gate and substrate separately from formation of the programming (30) and erase (28) tunneling elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.