Double stage sense amplifier for random access memories
US5023841A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1989 |
| Grant date | Jun 11, 1991 |
| Priority date | — |
| Expiry date | Feb 21, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In combination with an electronic memory of the type having a plurality of memory cells (CA, . . . CN) connected between two bit lines (BLT, BLC) having inherent bit line capacitances (C1, C2), there is disclosed an improved sense amplifier (15) comprised of two stages. A first stage (16) includes a first clocked latch (5) having an enable device (T5), gated by a first control signal (SSA) and bit switches (T6, T7) connected between the common nodes (6, 7) of said first clocked latch and said bit lines, and gated by a bit switch control signal (BS) to provide an output signal on first data lines (DLT, DLC). A second stage (17) includes a second clocked latch (20) having an enable device (T24) gated by a second signal (SL) and data switches (T28, T29) connected between second data lines (DT, DC) at the same potential as data output nodes (21, 22) of said second clocked latch and said first data lines (DLT, DLC). Said data switches (T28, T29) are gated by a data switch control signal (DS) which is derived from the bit switch control signal (BS), so that the first and second stages (16, 17) operate sequentially to amplify the data continuously along the sensing chain of the data path …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.