Six-way access ported RAM array cell
US5023844A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 1990 |
| Grant date | Jun 11, 1991 |
| Priority date | — |
| Expiry date | Feb 28, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory cell in a register file having multiple independent read ports and multiple independent write ports that support parallel instruction execution. The RAM cell consumes low power and conforms to a tight layout pitch to meet the needs of the random access memory. A single column line is used, with the storage latch device (M 11, M 12) increased in size to provide for the noise margin loss with reference to the prior art two-column design. A single n-device (M 1) is attached to the opposite side of the cell latch (M 11, M 12) to clear the cell prior to writing zeros into the cell. The registers that are to be written are first cleared in the PH2 of the first clock cycle, with the data written in PH1 of the second clock cycle which writes the ones. The zero bits are also written at this time, but they find a cell that already is in the zero state, having been cleared in PH2 of the first clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.