Interface circuit for data transmission between a microprocessor system and a time-division-multiplexed system
US5023870A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 1989 |
| Grant date | Jun 11, 1991 |
| Priority date | — |
| Expiry date | Jun 22, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The circuit of the present invention provides a signal which allows data to be transferred between a first synchronous system to a second synchronous system. Where the first synchronous system is a Time-Division-Multiplexing (TDM) system and the second synchronous system is a Microprocessor system. The transfer is allowed at the end of the assigned time slot provided that the microprocessor is not accessing the data. If the microprocessor is accessing the data, then the transfer is delayed for three clock cycles of the TDM clock. After the delay, if the microprocessor is still accessing the data, the transfer is delayed again. The delaying continues until the microprocessor is no longer accessing the data, at which time the transfer is allowed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.