Interlaced scan fault detection system
US5023875A · kind A · utility
10Cited by
10References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 1989 |
| Grant date | Jun 11, 1991 |
| Priority date | — |
| Expiry date | May 26, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A fault detection system 50 includes first and second serial data shift register stages 74, 94 which are connected to a logic circuit under test 106, and a third serial data shift register stage 84 which is logically connected between the first and second serial data sift register stages 74, 94. The fault detection system 50 permits all paths of the logic circuit under test 106 to be sensitized and allows for the detection of all propagation delay type faults at substantially the operational speed of the logic circuit under test 106.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.