Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
US5025365A · kind A · utility
115Cited by
9References
11Claims
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Key dates
| Filing date | Nov 14, 1988 |
| Grant date | Jun 18, 1991 |
| Priority date | — |
| Expiry date | Nov 14, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure describes a snooping coherency protocol for a multiprocessor network wherein every processor has its own private cache and bus interface means and the network is connected via a common system bus. Each processor has its own cache directory and image directory that duplicate each other non-atomically. The snooping protocol utilizes the duality of directories coupled with the non-atomicity of directory updates to maximize processor-cache availability and minimize processor-cache access times thus supporting high performance architectures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.