Self-calibrating analog to digital converter
US5027116A · kind A · utility
36Cited by
8References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1987 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | Feb 24, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/403
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self calibrating algorithmic analog-to-digital converter is disclosed for which the gain of the conversion loop is precisely adjusted and controlled by an array of switched capacitors such control being stored in a latch. The offset of the gain stage is reduced by reducing the amount of charge injected from the gate of the input zeroing MOS switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.