Cavity-down chip carrier with pad grid array
US5027191A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 1989 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | May 11, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10719
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention is an improved chip carrier assembly utilizing a cavity-down chip carrier with a pad grid array wherein the IC chip within the chip carrier is mounted against a surface opposite the PWB to which the chip carrier is attached such that heat transfer from the IC chip may occur along a short path to a heat sink such that a large heat transfer rate is possible. Furthermore, the apparatus utilizes an alignment and electrical connection means between the contact pads of the chip carrier and a PWB to which the chip carrier is attached to compensate for shrinkage variation which occurs during the chip carrier fabrication process. Furthermore, within the cavity of the chip carrier there is space for additional components such as a decoupling capacitors. This permits the design of an apparatus providing better heat transfer properties, more accurate contact pad locations and the option of including within the chip carrier components which in the past had been mounted outside of the chip carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.