Semiconductor input protection device
US5027252A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 1990 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | Oct 12, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
A semiconductor input protection device is disclosed which comprises a well type punch-through transistor consisting of a pair of parallel-opposed well layers through intermediation of a field oxide film, one of which is connected to an input terminal and the other to a reference potential. The device further comprises an impurity diffusion layer resistance with an end thereof connected to the input terminal. The lower limit distance between the opposed sides of the well layers to each other and the channel stopper is set to be smaller than that between the channel stopper and the input terminal-side well layer in the area where the latter and the impurity diffusion layer resistance intersect. The two lower limit distances depend on punch-through voltage, the width of the depletion layer in the well layer at applied punch-through voltage, and the junction disruptive strength of the well layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.