Decimation filter as for a sigma-delta analog-to-digital converter
US5027306A · kind A · utility
Inventors
Key dates
| Filing date | May 12, 1989 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | May 12, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0614
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A single stage multi-rate finite impulse response filter is used as the decimating filter for a sigma-delta analog-to-digital converter. The filter uses 2048 22-bit coefficient values to produce a sampled data output signal having a sampling rate of 48 KHz and a sample resolution of 16 bits from an input signal having a sampling rate of 3.072 MHz and a sample resolution of one bit. The filter uses a single read-only memory to hold the 2048 coefficient values. The coefficient values are distributed to eight four-way multiplexed accumulators by a circuitry which includes a signal multiplexer and a barrel shifter. The accumulators use unsigned arithmetic to calculate the output sample values. A value C0, representing a normalizing offset and gain applied to each of the coefficient values, is selected such that 2048 times C0 is a value which overflows the accumulator, leaving a value of zero in the accumulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.