Addressing for large dynamic RAM
US5027329A · kind A · utility
5Cited by
2References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1989 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | Dec 4, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM semiconductor memory chip comprised of a matrix of rows and columns having a bit storage cell at each location, means for receiving row and column address bits in multiplexed form on a single address bus, the multiplexing arrangement being such that the number of column address bits exceeds the number of row address bits, whereby a system using the DRAM memory chip has access to an enlarged page size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.