Asynchronous time division communication system
US5027351A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1989 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | Sep 18, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An asynchronous time division communication system having at least one station including a buffer and an associated processor for writing data packets into said buffer at a sending clock frequency, and for reading data packets from said buffer at a receiving clock frequency. The processor is further capable of assessing the real packet filling level of the buffer and adjusting the receiving clock frequency in corresponding relationship to the assessed real packet filling level. The processor calculates a mean packet filling level after a measured time has elapsed by using the mean of m successively assessed real packet filling levels of said buffer and using the calculated mean packet filling level for adjusting the receiving clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.