Electronic memory testing device
US5027354A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1989 |
| Grant date | Jun 25, 1991 |
| Priority date | — |
| Expiry date | Nov 6, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A verification circuit comprising a CPU, a RAM connected with the CPU and a data A is written therein, an I/O port connected at input thereof an output of said CPU and an output of the RAM for receiving the data A from the RAM, a plurality of drivers each connected with the output of the RAM via said I/O port, the drivers being turned on while a control signal is "1" and turned off while the control signal is "0", a PROM connected with an output of the driver, the data A written in said PROM when the control signal is "1", and a data B to be compared with the data A is read from the PROM when the control signal is "0", a reference voltage having H and L levels, a plurality of analog switches each issuing H level of the reference voltage while the data A is "1" and L level of the reference voltage while the data A is "0", and a plurality of comparators each having one input terminal connected with an output of the analog switch and the other input terminal connected with the output of the PROM. The verification circuit may further include a plurality of the exclusive OR circuit and a gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.