Etched back edge isolation process for heterojunction bipolar transistors
US5028549A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1989 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Apr 10, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/103
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of isolating individual heterojunction bipolar transistors (HBTs) on a wafer increases the current gain which can be obtained when using proton implantation to isolate the transistor. The photoresist pattern which is used to cover the transistor location during isolation implantation is undercut when etching the cap layer. A dielectric is then deposited on the etched surface, including the undercut portion. The photoresist is lifted off and an HBT is fabricated on the wafer in the area which is not covered by the dielectric. The dielectric on the undercut portion confines the emitter current to a region slightly removed from the isolation implant and provides improved current gain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.