High CMOS open-drain output buffer
US5028819A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1990 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Jun 8, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018571
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS N-channel, open-drain, pull-down buffer circuit is capable of pulling down voltages on an external pad in excess of the breakdown voltage of the individual N-channel field effect transistors in the buffer circuit. The circuit may be fabricated as part of a CMOS interated circuit in an industrial standard 1.5 microns CMOS process. The higher voltage acceptance is effected by using two open-drain N-transistors in series such that the external voltage is divided among the two transistors. A parallel high voltage circuit to the external pad can be independently optimized to provide a lower impedance path and a higher endurance for electrostatic discharge. While the two-transistor voltage divider exposes one of the transistor' gate to ESD via another external terminal, enhanced ESD protection is effected by having a resistor in series between the gate and the external terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.