Circuit arrangement for processing analogue electrical signals
US5028822A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 22, 1989 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Nov 22, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement for processing sampled analogue electrical signals comprises means for combining (9) in predetermined proportions on input sample current in the present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods and means for deriving the processed output signal as or from the combined current produced by the combining means in successive sample periods. The circuit arrangement further comprises means for scaling a current which comprises a first branch (T1) for receiving a current to be scaled, second and third branches (T2,T3) for producing first and second sub-output currents which are proportional to the received current, means for forming the difference (2) between the first and second sub-output currents, and means for feeding the difference current to the output (3) of the current scaling means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.