Ratiometric measurement circuit with improved noise rejection
US5028874A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 1989 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Nov 1, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/25
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A noise rejection circuit improves the signal-to-noise ratio of a ratiometric measurement circuit. A first operational amplifier produces a scaled-up voltage proportional to a low reference voltage. The scaled-up voltage is applied to a series connected reference resistance, whose value is known, and a resistance whose value is unknown and is to be measured. A parameter voltage formed across the resistance is applied to second operational amplifier acting as a buffer. A buffered parameter voltage is scaled down by a voltage divider. The scaled-down voltage is applied to a ratiometric converter, that produces an output representative of the unknown resistance value. The ratio of a first pair of resistors that determines the gain of the first operational amplifier is the same as the ratio of a second pair of resistors that form the voltage divider, such that the low reference voltage is scaled up and the parameter voltage is scaled down by the same factor. The ratiometric converter operates from a low power supply voltage and consumes low amounts of power. The first and second amplifiers are CMOS operational amplifiers that, despite operating from a relatively high power supply volta…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.