Circuit arrangement for a fast Fourier transform
US5028877A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1989 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Dec 21, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit arrangement for the implementation of a fast discrete Fourier transform in real time through the controlled operation of cross-linked butterfly, or kernel, operators. The circuit arrangement will successively transmit the two halves of a sequence of complex input words through a series-parallel input register and an interim data storage to a plurality of butterfly operators which operate in parallel, whose outputs are switchable by a multiplexer for recursive linkage with the interim storage or, in essence, for the delivery of the frequency range-output words to a parallel-series output register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.