Patent · US Expired

Dual memory timing system for VLSI test systems

US5028878A · kind A · utility

1Cited by
4References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 13, 1989
Grant dateJul 2, 1991
Priority date—
Expiry dateNov 13, 2009

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/31922
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A timing system using shared address generator(s) to address memories that form the basis of each pin's timing reference generator can reduce the amount of hardware required to implement a "Timing Generator Per Pin" architecture in a VLSI tester by at least 50%.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.