Direct digital synthesizer driven phase lock loop frequency synthesizer with hard limiter
US5028887A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 1990 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Mar 29, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered and amplitude limited to reduce spurious noise. In one embodiment, the DDS frequency synthesizer is coupled to a phase lock loop which receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal. In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size. The synthesizer output frequency is a function of the input reference frequency, the number of bits in the digital word of the frequency control signal and the DDS step size as determined by the frequency control signal. Optional dividers may be provided in t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.