Digital correction of gain mismatch in a sigma delta modulator
US5028924A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 1990 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Mar 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/418
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oversampling analog-to-digital converter is responsive to an analog input signal for providing a digital output signal representative of the magnitude of the analog input signal at an output bus. The analog input signal is quantized through a sigma delta modulator stages for providing first and second digital output signals which are recombined through at least first and second digital integrators and at least first and second digital differentiators of a low pass comb filter for providing the digital output signal. The first digital output signal controls the application of either a digital correction signal or digital zeroes to the least significant portion of a predetermined number of accumulator cells of the first digital integrator thereby substituting the digital correction signal for the digital output signal to weight the latter's contribution and compensate for the quantization error which increases the resolution of the digital output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.