Adaptive array processor
US5028931A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 1990 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | May 24, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S7/36
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An off-line processor arrangement for a broadband accelerated convergence adaptive antenna array wherein signals from a plurality of antenna elements are applied to respective identical tapped delay lines (T) the outputs of which are fed through individual signal weighting means to a beamforming network (BFN), the arrangement including one or more lattice filter means (LF) to which the auxiliary antenna element signals are applied together with the output response of the beamforming network to compute sets of weight correction vectors (* W) with which to update weight coefficients and means for storing said updated coefficients, said stored coefficients being applied to the individual signal weighting means to weight the outputs of the tapped delay lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.