Programmable pipeline for formatting RGB pixel data into fields of selected size
US5029105A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1987 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Aug 18, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel map into regularly offset permutations on groups of RAM (Random Access Memory) address and data line assignments. Changing the mapping of (X, Y) pixel addressed to RAM addresses for the groups changes the size and shape of the tiles. A pixel data/partial address multiplexing method based on programmable tile size reduces the number of interconnections between a pixel interpolator and the frame buffer without significantly increasing the number of bus cycles needed to transfer the information. A programmable pipelined shifter allows the dynamic alteration of the mapping between bits of the RGB (red, green, blue) intensity values and the planes of the frame buffer into which those bits are stored, as well as allowing those values to be truncated to specified lengths. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separate cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.