Semiconductor memory device
US5029330A · kind A · utility
23Cited by
2References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 12, 1989 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Jun 12, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multibit test mode for a dynamic RAM, a plurality of complementary data lines are simultaneously connected to the complementary common data lines and the levels of noninversion signal lines and inversion signal lines of the complementary common data lines are compared with a predetermined reference voltage, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.