DC power switch with inrush prevention
US5030844A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1990 |
| Grant date | Jul 9, 1991 |
| Priority date | — |
| Expiry date | Jun 25, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S323/908
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DC power switch (10) for a capacitive load (11) has a main transistor (Q1) in series with the load between positive and negative DC bus terminals (B.sup.+, B.sup.-). A secondary transistor (Q2) and a resistor (R.sub.1) are connected in series and this series connection is connected in parallel to the main transistor (Q1). A control circuit (20; 50) is connected to the main and secondary transistors (Q1, Q2) and controls them. In response to an enable signal (26), the secondary transistor (Q2) is initially turned on such that it and the resistor provide the initial charging current for the capacitor load (11) and subsequently the secondary transistor is turned off and the main transistor is turned on such that it provides the subsequent current required by the load. This configuration minimizes the power dissipation ratings required for the transistors while balancing this requirement with the relative rapid providing of charging current for the capacitive load. Fault detection circuitry (30-33) makes sure both the main and secondary transistors are off and interrupts the supply of DC power to the load (11) in the event of a detected fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.