Test circuit for non-volatile storage cell
US5031152A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1989 |
| Grant date | Jul 9, 1991 |
| Priority date | — |
| Expiry date | Sep 29, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.