MOS semiconductor memory device having sense control circuitry simplified
US5031153A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1989 |
| Grant date | Jul 9, 1991 |
| Priority date | — |
| Expiry date | Dec 12, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4099
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An MOS semiconductor memory device includes memory cell matrices. Each matrix is constituted with memory cells and noise cancellers. Each memory cell is connected, at an intersection between a pair of bit lines and a word line, between either one of the bit lines and the word line. The word line controls read and write operations of the memory cell. The noise canceller is connected, at an intersection between a pair of bit lines and a dummy word line, between either one of the bit lines and the dummy word line. The dummy word line enables the noise canceller. The memory cell matrices form groups of memory cells into which the cells are grouped in accordance wtih addresses. The dummy word line and the word line have substantially identical characteristics. The dummy word line possesses parasitic resistance and capacitance to delay by a first predetermined period of time a signal to enable the noise canceller. The memory device further includes sense amplifier circuits connected between the pair of bit lines of the memory cell matrices for amplifying a potential difference between the bit lines in response to an enable signal, and a sense control circuit connected to the dummy word l…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.