Coplanar packaging techniques for multichip circuits
US5032543A · kind A · utility
36Cited by
13References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1988 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | Jun 17, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for assembling and interconnecting large, high-density circuits from separately fabricated components, where conventional preassembly device testing, and conventional production techniques, can be employed in an uncomplicated process. A plurality of semiconductor chips are applied connection-side down to a temporary soluble substrate and then encapsulated. The temporary soluble substrate is then dissolved, exposing the connection side of the chips, to which electrical connections can then be made.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.