High performance attenuator configuration
US5032801A · kind A · utility
14Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1990 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | Jul 31, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high performance attenuator configuration divides a signal path into a plurality of parallel attenuator paths, each path having a predetermined attenuation value. A switch for each attenuator path is provided to couple selectively one of the attenuator paths to an input connector. Each attenuator path has an FET buffer amplifier, and the outputs of the FET buffer amplifiers are input to an electronic switch or multiplexer. The electronic switch selects the FET buffer amplifier output to be passed on to an output drive circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.