High voltage planar edge termination using a punch-through retarding implant
US5032878A · kind A · utility
21Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 2, 1990 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | Jan 2, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/106
Abstract
A high voltage semiconductor structure having multiple guard rings, wherein guard rings farthest from a main junction are spaced further from each other than are guard rings closer to the main junction is provided. An enhancement region, which is of an opposite conductivity type from the guard rings, is formed between the guard rings to increase punch-through voltage between the guard rings, thereby increasing the breakdown voltage of the device. The enhancement region and close guard ring spacing result in a fine gradation of electric field and high punch-through breakdown voltage between guard rings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.