Semiconductor pin device with interlayer or dopant gradient
US5032884A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1990 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | Feb 7, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
Abstract
A semiconductor device comprising a pin-type or nip-type amorphous-containing semiconductor layers; characterized in that (1) at least one interlayer made of semiconductor or insulator having higher electrical resistivity than a semiconductor which adjoins the interlayer is/are interposed between semiconductor layers or between a semiconductor and an electrode, (2) an amount of dopant in a p-type or n-type layer is least at a junction interface of p/i or n/i and increases gradually toward a junction interface of p/electrode or n/electrode, or (3) a p-type semiconductor layer being the same conductive type as the p-type semiconductor and having higher impurity density and/or an n-type semiconductor layer being the same conductive type as the n-type semiconductor layer and having higher impurity density is/are interposed between the p-type semiconductor layer and the electrode at the side of the p-type semiconductor layer and/or between the n-type semiconductor layer and the electrode at the side of the n-type semiconductor layer. According to the semiconductor device of the present invention (in the case of (1) or (2)), large Voc and electric current at a specific voltage can be obt…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.