Wiring structure in a wafer-scale integrated circuit
US5032889A · kind A · utility
5Cited by
1References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1990 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | Sep 20, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer-scale integrated circuit includes a plurality of functional blocks, a plurality of respectively corresponding connection terminals being provided in each of the functional blocks. Respectively corresponding pluralities of layered wirings and bonding wires interconnect predetermined, respective ones of said corresponding connection terminals in parallel for supplying power source and other voltages in common to the plurality of functional blocks. The parallel interconnections by the layered wirings and bonding wires, due to different, respective failure modes, affording increased reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.