Semiconductor memory device and manufacturing method thereof
US5032891A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1990 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | May 15, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
Disclosed is a semiconductor memory device comprising an SOI substrate in which a semiconductor film is formed on a semiconductor substrate with an insulating film interposed therebetween. A memory cell structure is formed by a switching MOS transistor formed in the SOI substrate and an Esaki diode is positioned on the MOS transistor. The memory device also comprises a memory cell provided with a plurality of tunnel diodes connected to one of the impurity regions constituting the FET formed in the semiconductor substrate, and another memory cell provided with an Esaki diode formed in an self-alignment by a solid phase diffusion. In manufacturing the semiconductor memory device, the MOS transistor and the Esaki diode, which collectively form a memory cell, are integratedly formed one upon the other. The MOS transistor is formed in a semiconductor substrate using an SOI structure so as to prepare a memory cell which does not include a parasitic pn-junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.