Device for timing interrupt acknowledge cycles
US5032982A · kind A · utility
19Cited by
17References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 1990 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | May 7, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral device containing a control circuit with internal timing which enables it to independently adjust the timing of an interrupt acknowledge cycle. The circuit senses a timing signal from the CPU and asserts a control signal to suspend the operation of the CPU for a predetermined period of time. The predetermined period of time is customized to the peripheral so that when the CPU is re-activated and reads from the bus, a valid interrupt vector will have been put out by the peripheral.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.