Matrix memory with redundancy and minimizes delay
US5033024A · kind A · utility
15Cited by
1References
7Claims
0Family size
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Key dates
| Filing date | Dec 20, 1989 |
| Grant date | Jul 16, 1991 |
| Priority date | — |
| Expiry date | Dec 20, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated matrix memory includes standard sub-blocks and a redundant block. Each of the standard sub-blocks has a fixed number of standard sub-blocks, and the redundant block has one or more redundant sub-blocks. For addressing there is provided a detector for the address of a faulty standard sub-block. In that case a redundant sub-block is selected. Selection is realized by way of a sub-bus which forms part of the data path. Thus, a redundant system is achieved in which delay is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.