Semiconductor device with reduced side wall parasitic device action
US5034788A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 25, 1990 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | Oct 25, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6706
Abstract
A semiconductor device having a sapphire substrate on which is formed a localized island of polysilicon, the island having side walls which extend away from a surface of the substrate. A field effect transistor is formed in the island and a doped polysilicon fillet is interposed between the gate region and the substrate. In addition the electrical potential of the polysilicon fillet is controlled with respect to the source region. The control of the electrical potential enables the premature turn on characteristics of the device to be reduced by the polysilicon fillet forming a secondary gate electrode on the side walls, and because these secondary gates are at source potential the parasitic edge transistor present in the side wall is always turned off. A modified device has an independent side gate bias arrangement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.