Cache memory device with fast data-write capacity
US5034885A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1989 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | Mar 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A copy-back type cache memory device using a delayed wait method capable of completing a data-write process in one process cycle. The device includes single word memory means for storing the single word of the selected data in a data memory means when an access for a data-write is made, the single word being located at the address in the data memory means corresponding to the processor address; and copy-back memory means for restoring the superseded data along with other data together with which the superseded data forms a block, so that the block can be reorganized in its original state before the data-write process takes place. The device may alternatively include an address latch means for delaying transmission of a processor address from the processor to the data memory means by a predetermined number of process cycles when access by the processor is for a data-write process; and a data latch means for delaying transmission of a processor data from the processor to the data memory means by the predetermined number of process cycles when access by the processor is for a data-write process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.