Dynamically configurable signal processor and processor arrangement
US5034907A · kind A · utility
16Cited by
8References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1990 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | Nov 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable digital signal processor usable in a variety of configurations and controlled by stored coefficients and control words which are addressable to be provided to a plurality of processing sections as often as once per clock cycle. The processor arrangement is suitable for use as a decoder of multiple analog component (MAC) television signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.