Signal processing circuit for multiplication
US5034912A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1990 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | Jan 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06J1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplication processing circuit requiring no digital-analog converter includes a circuit for multiplying a digital multiplication coefficient by a digital multiplicand and outputting the result of multiplication as an analog current signal. The multiplication processing circuit includes a circuit for decoding the digital multiplication coefficient to generate one or a plurality of control signals, a circuit responsive to the digital multiplicand and to the generated control signal for generating a signal indicating, in decimal notation, the result of multiplication of the digital multiplication coefficient by the digital multiplicand, and a circuit for converting the signal indicating the result of multiplication into an analog current signal of a corresponding magnitude. Each of the control signals indicates at least one digital multiplication coefficient in decimal notation. The circuit for generating the signal indicative of the result of multiplication includes a circuit for logically processing, by logic gates, the control signal and the digital multiplicand. The logic gate circuit includes a circuit for detecting coincidence/non-coincidence between a pattern of the genera…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.