Computer system including a page mode memory with decreased access time and method of operation thereof
US5034917A · kind A · utility
103Cited by
13References
5Claims
0Family size
Inventors
Key dates
| Filing date | May 26, 1988 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | May 26, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is provided in which memory access time is substantially reduced. After row address strobe (RAS) and column address strobe (CAS) signals are used to select a particular address in a memory during a first memory cycle, the addressed data is latched for later transfer to a data bus. A CAS precharge of the memory is then conducted after such latching and prior to the end of the first memory cycle before the commencement of the second memory cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.