Cross point array memory device
US5034920A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 3, 1990 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | May 3, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array layout using complementary bitlines connected to a single sense amplifier. Extending from the sense amplifier, bitlines which are unconnected are extended to the middle of the array. One complementary bitline is then connected to a series of memory cells extending away from the sense amplifier. The other complementary bitline loops back and is connected to a set of memory cells extending back toward the sense amplifier. The first bitline section extending from the sense amplifier may be advantageously formed in a metal layer above the substrate thereby occupying no space in the substrate itself. All noise generated on the first sections of the bitlines will be canceled by the complementary parallel structure of the bitlines. Because the second sections of the bitlines are laterally separated, a wordline passing across each of the second sections addresses a singel memory cell. Therefore an optimally compact cross-point memory array may be fabricated. Using the described techniques an optimally compact array having an improved signal to noise characteristic may be fabricated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.