Non-volatile semiconductor memory
US5034926A · kind A · utility
42Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1989 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | Aug 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a non-volatile semiconductor memory of this invention, a memory cell array constituted by a plurality of memory cells is divided into a plurlaity of blocks, and erase lines which are common to the respective blocks and independent from each other are arranged. In the data write mode, a predetermined voltage is applied to only the erase line connected to a selected one of the blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.