VLSI bipolar transistor process
US5036016A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 1989 |
| Grant date | Jul 30, 1991 |
| Priority date | — |
| Expiry date | Feb 21, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/096
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bipolar VLSI process includes masking and patterning, implanting a P+ channel stop and locally oxidizing a lightly P-doped, monolithic silicon substrate to define a collector region. An N-type collector is implanted and the implants are diffused to form a shallow gradient P-N junction. Then, device emitter, base and collector contact features are photolithographically defined by two openings spaced along the length of the collector region. The collector region is formed in a keyhole shape with a wider end portion encompassed by the collector contact feature and adjoining opening and a narrower opposite end portion which includes the base contact and emitter features and intervening opening. Low resistivity P- and N-type regions are implanted in the substrate in the openings; the openings are covered by local oxidation; and the substrate surface region are exposed in the adjoining contact features. The active transistor and the collector, base and emitter contacts are thereby self-aligned within the collector region. A single polysilicon layer is used to form base, collector and emitter contacts and a triple diffused transistor. Portions of the substrate silicon and polysilicon ar…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.