Master/slave sequencing processor
US5036453A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1989 |
| Grant date | Jul 30, 1991 |
| Priority date | — |
| Expiry date | Aug 2, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array processor includes a master array controller and sequencer (12) and a plurality of slave processors (20a)-(20n). The master generates sequencing commands for sequencing instruction flow in each of the slave processors. The slave processors generate addresses for associated memories (34a)-(34n). The data outputs of the memories are interfaced through a cross point switch (22) to a slave data processor (24). The master (12) is operable to initialize all of the slave devices to a starting address for an internal routine and sequence the instruction flow therein in a synchronous and parallel manner to execute a particular task.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.