System and method for reducing power usage by multiple memory modules
US5036493A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 1990 |
| Grant date | Jul 30, 1991 |
| Priority date | — |
| Expiry date | Mar 15, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer memory system has multiple memory banks, only one of which can be accessed at any one instant in time. A memory bank decoder determines which of the memory banks is being accessed. The decoded bank enable signals generated by the decoder are used to send memory clocking signals only to the memory bank which is being accessed. In addition, each memory bank includes a clocked address signal buffer and a clocked data signal buffer. Clock signals are sent only to the address and data buffers in the memory bank which is being accessed. As a result, only the selected memory bank has its address and data buffers updated. All the other memory banks remain in a quiescent state, because no control signal, address signals, or data signals are sent to those memory banks. This eliminates the energy usage that would otherwise be associated with the idle memory banks, including both the energy used by the memory chips in the idle memory banks, as well as the energy associated with changing the state of the address and data lines connected to those memory chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.