Construction process for a self-aligned transistor
US5037505A · kind A · utility
3Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 20, 1990 |
| Grant date | Aug 6, 1991 |
| Priority date | — |
| Expiry date | Mar 20, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
Abstract
Disclosed is a device enabling a transistor of submicronic gate length to be constructed using optical means of masking. The process includes a stage during which a resin, deposited on a wafer of semiconducting materials, is etched in order to isolate a pattern as a future gate mask. The mask is eroded, and a layer of silica deposited. Because of the erosion, the sides of the pattern and of the mask are inclined. After etching of the layer of silica and the masking resin, there remain therefore two silica masks whose sloping sides leave a submicronic aperture, through which the gate is deposited.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.