Carriers for electrical components in transistor outline packages
US5038101A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 1990 |
| Grant date | Aug 6, 1991 |
| Priority date | — |
| Expiry date | Mar 15, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/0433
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Carriers for electronic components in transistor outline packages with terminals arranged in circular or rectangular arrays. The carrier has a conductive frame including a planar portion, side rails and a housing section disposed along an axis transverse to the planar section. The housing contains an insert of insulating material with apertures disposed in an array corresponding to the terminal array thereby to grip at least some of the terminals and electrically isolate those terminals from each other. The insert has a length along the transverse axis that is at least coextensive with the terminals thus to isolate the terminals completely. A portion of the insert extends along the planar surface and the insert is open to receive the terminal test leads or other mechanisms for testing the component. Specific embodiments for TO packages with a different terminal arrays are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.