High speed digital packet switching system
US5038343A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 1990 |
| Grant date | Aug 6, 1991 |
| Priority date | — |
| Expiry date | Jun 20, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A 3-stage switching system is provided for generating, i.e. finding, reserving and setting, path from one switch entrance port (1) to at least one switch exit port (transmit side) for asynchronously received and buffered data cells. While an Nth cell is being transferred, control means (36) generate a control word including the switch exit port address for cell (N+1)th to be subsequently transferred. Said control word is used to find and reserve a path through the switch on a stage-by-stage basis, and then set said path, if any, using a fed back acknowledgement. The (N+1)th cell path generation is performed during cell N transfer, on a cycle stealing basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.