Fast sample and hold circuit configuration
US5039880A · kind A · utility
10Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1990 |
| Grant date | Aug 13, 1991 |
| Priority date | — |
| Expiry date | Apr 24, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/303
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sample and hold circuit configuration for differential signals with reduced holding capacity includes an amplifier in which the same current ratios prevail in the collector circuit and in the emitter circuit. The base currents are discharged through additional transistors and therefore the same currents flow and equal voltage ratios prevail in the collector and emitter resistors, and an additional diode is connected in each collector circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.